Synchronous residual time stamp for timing recovery in a broadband network

ABSTRACT

A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2 P  possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range. At the destination node, a pulse signal is derived in which the periods are determined by the number of network clock cycles represented by the received RTSs. This pulse signal is then multiplied in frequency by N to recover the source node service clock.

.Iadd.This application is the parent application of reissue application09/292,668 filed Apr. 16, 1999. .Iaddend.

BACKGROUND OF THE INVENTION

This invention relates to timing recovery of a source node service clockfrequency at a destination node in a broadband asynchronous transfermode (ATM) network where the source and destination nodes receivereference timing signals derived from a single master clock.

Asynchronous Transfer Mode (ATM) is a packet oriented technology for therealization of a Broadband Integrated Services Network (BISDN). By usingATM, network resources can be shared among multiple users. Moreover,various services including voice, video and data can be multiplexed,switched, and transported together under a universal format. Fullintegration will likely result in simpler and more efficient network andservice administration and management. However, while conventionalcircuit-switching is optimized for real-time, continuous traffic, ATM ismore suitable for the transport of bursty traffic such as data.Accommodation of constant bit rate (CBR) services is, however, animportant feature of ATM, both for universal integration and forcompatibility between existing and future networks. In the transport ofa CBR signal through a broadband ATM network, the CBR signal is firstsegmented into 47-octet units and then mapped, along with an octet ofATM Type I Adaptation Layer (AAL) overhead, into the 48-octet payload ofthe cell. The cells are then statistically multiplexed into the networkand routed through the network via ATM switches.

It is essential to the proper delivery of such CBR service traffic in abroadband network that the clock controlling the destination node bufferbe operating at a frequency precisely matched to that of the servicesignal input at the source node in order to avoid loss of informationdue to buffer over- or under-flow. However, unlike the circuit-switchedtransport of service data wherein the clock frequency at the destinationnode may be traced directly back to that of the source node by theregular, periodic arrival of the CBR traffic, transport in an ATMnetwork inherently results in cell jitter, i.e. the random delay andaperiodic arrival of cells at a destination node, which essentiallydestroys the value of cell arrival instances as a means for directlyrecovering the original service signal input frequency.

Such cell jitter, generally the result of the multiplexing of transportcells in the broadband network and the cell queuing delays incurred atthe ATM switches in the network, is substantially unpredictable. Thus,little is known about the cell arrival time beyond the fact that theaverage cell delay is a constant, assuming that the ATM network providessufficient bandwidth to ensure against loss of cells within the network.As a means for closely approximating the service signal frequency at thedestination node, some consideration had previously been given toutilizing a direct extension of circuit-switched timing recoverypractices which rely entirely upon a buffer fill signal as the basis forrecovery of the source timing. However, due to the lack of knowledge ofstatistics of the cell jitter, this approach would have required aphase-locked loop with very low cut-off frequency (in the order of a fewHz) and would thus have resulted in excessive converging time anddegradation of jitter and wander performance.

A number of schemes have been proposed to improve upon such aconventional manner of recovering service timing in the presence of celljitter, yet none has achieved this end economically and withoutextensive control systems of notable complexity. Singh et al., forexample, in "Adaptive Clock Synchronization Schemes For Real-TimeTraffic In Broadband Packet Networks," 8th European Conference onElectrotechnics, Stockholm, Sweden, June 1988, and "Jitter And ClockRecovery For Periodic Traffic In Broadband Packet Networks," IEEEGlobecom '88, Florida, December 1988, have proposed algorithms whichattempt to more closely estimate cell jitter statistics and derivetiming recovery from those indications. These adaptive approaches,suggested to be applicable to both synchronous and non-synchronousnetworks, rely upon the interaction of increasingly complex algorithmswhich would require the noted extensive controls for implementation.

These prior art schemes described above can be classified asnon-synchronous techniques, which are based on the simple fact that theexpected value of the network cell jitter is zero and thus rely on phasefiltering. Synchronous techniques, on the other hand, utilize the factthat common timing is available at both the transmitter and thereceiver. In a synchronous broadband ATM network, such as theSynchronous Optical Network (SONET) prescribed by American NationalStandard, ANSI T1.105-1988, "Digital Hierarchy Optical Interface Ratesand Formats Specification," Mar. 10, 1988, the network source anddestination node control clocks are synchronized to the same timingreference. As a result, there is no necessity for relying upon anyextraneous phenomenon such as instants of cell arrival to provide adatum base for determining the relative frequencies of those controlclocks. The effect of cell jitter caused by multiplexing and switchingdelays in the network is therefore of little consequence in anyprocedure for circuit transporting CBR service, which is based, as isthe present invention, on an actual synchrony of node timing. Thus beingdevoid of concern for cell jitter, this process is free to simplydetermine the difference in frequency between the CBR service signalinput at the source node and the source/destination node timingclock(s).

U.S. Pat. No. 4,961,188 issued on Oct. 2, 1990 to Chi-Leung Lau,co-inventor herein, discloses a synchronous frequency encoding technique(SFET) for clock timing in a broadband network. The SFET takes advantageof the common timing reference at both the source and the receiver. Atthe source, the asynchronous service clock is compared to the networkreference clock. The discrepancy between properly chosen submultiples ofthe two clocks is measured in units of a preassigned number of slipcycles of network clock. This clock slip information is conveyed via aFrequency Encoded Number (FEN) which is carried in the ATM AdaptationLayer (AAL) overhead. At the receiver, the common network clock and theFEN are used to reconstruct the service clock. This timing recoveryprocess does not rely on any statistics of the cell jitter except thatit has a known, bounded amplitude. Therefore, the recovered clock hasjitter performance comparable to that of the circuit-switched network.

An alternative proposed approach is known as Time Stamp (TS). In theTime Stamp approach (see, for example, Gonzales et al, "Jitter Reductionin ATM Networks", Proceedings ICC'91, 9.4.1-9.4.6), the network clock isused to drive a multi-bit counter (16-bits in the proposal), which issampled every fixed number of generated cells (e.g., 16). Thus, a fixednumber, N, of service clocks cycles is used as the measuring yardstick.The sampled value of the 16-bit counter is the TS that inherentlyconveys the frequency difference information. Because of the size of theTS (2 octets), it has been proposed that the TS be transmitted via theConvergence Sublayer (CS) overhead. Thus the TS is a 16-bit binarynumber occurring once every N service clock cycles. Differences insuccessive TSs represent the quantized values of M, where M is thenumber of network clock cycles during the fixed TS period. At thereceiver, the TS period is reconstructed from the received TSs and thenetwork clock. A free-running 16-bit counter is clocked by the networkclock and the output of the counter is compared to the received TSswhich are stored in a TS FIFO. A pulse is generated whenever there is amatch between the TS and the 16-bit counter. The service clock isrecovered by supplying the resultant pulse stream as the referencesignal to a multiply-by-N phase locked loop (PLL).

A comparison of the SFET approach and the TS approach reveals advantagesand disadvantages for each. In the SFET approach there is a relativelystringent requirement on the derived network clock since it must beslightly larger than the service clock. Advantageously, however, aconvergence sublayer is not required to transmit the FEN and only smalloverhead bandwidth is required to transmit the necessary information. Onthe other hand, the TS approach is more flexible in that it does notrequire stringent relationships between the service clock and thenetwork derived clock and can therefore support a range of service bitrates. Disadvantageously, however, a rigid convergence sublayerstructure is required to transmit the TS, which adds complexity andmakes inefficient use of the overhead bandwidth.

An object of the present invention is to achieve synchronous timingrecovery with an approach that has the advantages of both the SFET andTS approaches, specifically, the efficiency of SFET and the flexibilityof TS.

SUMMARY OF THE INVENTION

As described hereinabove, the TS approach requires a large number ofbits (16-bits in the example), to represent the number of network clockcycles within a time interval defined by a fixed number (N) of serviceclock cycles. In accordance with the present invention, the number ofbits required to represent the number of network clock cycles withinthat time interval is substantially reduced. This is possible throughthe realization that the actual number of network clock cycles, M (whereM is not necessarily an integer), deviates from a nominal known numberof cycles by a calculable deviation that is a function of N, thefrequencies of the network and service clocks, and the tolerance of theservice clock. Specifically, therefore, rather than transmitting adigital representation of the quantized actual number of network clockcycles within the interval, only a representation of that number as itexists within a defined window surrounding an expected, or nominal,number of network clock pulses is transmitted from a source node to adestination node in an ATM network. This representation will be referredto hereinafter as the Residual Time Stamp (RTS). By selecting the numberof bits, P, so that all 2_(P) possible different bit patterns uniquelyand unambiguously represent the range of possible numbers of networkclock cycles within the fixed interval that is defined by N serviceclock cycles, the destination node can recover the service clock fromthe common network clock and the received RTS.

At the source node, a free-running P-bit counter counts clock cycles ina clock signal derived from the network clock. The service clock, whichis derived from the incoming data signal to be transmitted over the ATMnetwork, is divided by the factor of N to produce a pulse signal havinga period (the RTS period) which defines the time interval for measuringthe number (modulo 2^(P)) of derived network clock pulses. At the end ofeach RTS period, the current count of the free-running P-bit counter issampled. That sampled value is the RTS, which is transmitted via theadaptation layer. Since the service clock from which the RTS period isdefined and the derived network clock are neither synchronized norintegrally related in frequency, the actual number of derived networkclock cycles in a RTS period is unlikely to be an integer. Thus, whensampled at the end of each RTS period, the increment in the count of theP-bit counter is a quantized version of the count (modulo 2^(P)) ofpulses in the RTS interval as modified by any accumulated fractionalcounts from a previous interval.

At the destination node, after the AAL is processed, the successive RTSsare converted into a pulse signal which has periods between pulsesdefined by the fixed integral numbers of derived network clock pulsesthat correspond to the conveyed RTS periods. Specifically, afree-running P-bit counter is driven by the derived network clock. Acomparator compares this count with a stored received RTS and produces apulse output upon a match. Since the count of the P-bit counter matchesthe stored RTS every 2_(P) derived network clock cycles, comparatoroutput pulses that do not actually represent the end of the RTS periodare inhibited by gating circuitry. This gating circuitry includes asecond counter that counts the derived network clock cycles occurringsince the end of the previous RTS period. When this second counterreaches a count equal to the minimum possible number of derived networkclock pulses within an RTS period, the next comparator pulse outputproduced upon a match between the RTS and the count of the P-bitcounter, is gated-through to the output and resets the second counter.The resultant gated through output pulse stream drives a multiply-by-Nphase locked loop to recover the service clock.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 are timing diagrams showing the RTS concept of the presentinvention;

FIG. 2 is a block diagram showing apparatus, in accordance with thepresent invention, for generating the RTS at the source node of an ATMnetwork;

FIG. 3 is a block diagram showing apparatus, in accordance with thepresent invention, for reconstructing the service clock at thedestination node of an ATM network; and

FIG. 4 are timing diagrams showing the gating function at the apparatusof FIG. 3.

DETAILED DESCRIPTION

The concept of the Residual Time Stamp is described with reference toFIG. 1. In FIG. 1, and in the description hereinafter, the followingterminology is used:

f_(n) --network clock frequency, e.g. 155.52 MHz;

f_(nx) --derived network clock frequency, ##EQU1## where x is a rationalnumber; f_(s) --service clock frequency;

N--period of RTS in units of the service clock (f_(s)) cycles;

T_(n) --the n-th period of the RTS in seconds;

±ε--tolerance of the source clock frequency in parts per million;

M_(n) (M_(nom), M_(max), M_(min))--number of f_(nx) cycles within then-th (nominal, maximum, minimum) RTS period, which are, in general,non-integers.

As can be noted in FIG. 1, during the n-th period, T_(n), correspondingto N service clock cycles, there are M_(n) network derived clock cycles.As aforenoted, since the service clock and the network clock are neithersynchronized nor integrally related in frequency, this number of derivednetwork clock cycles is not an integer. Since all practical timingrecovery techniques transmit only integer values, the fractional part ofM_(n) must be dealt with. Simple truncation or rounding of thefractional part in each RTS time slot is not permissible, as this wouldlead to a "random walk" type error accumulation. Rather, it is necessaryto accumulate the fractional parts at the transmitter and use theaccumulated value to modify the transmitted integer quantity. Since itis most convenient to generate RTS by an asynchronous counter, as willbe described hereinafter in conjunction with the description of FIG. 2,a "truncation" operation is natural, reflecting the fact that anasynchronous counter's output does not change until the subsequent inputpulse arrives. To formalize these notions, S_(n) is defined as thetruncated value of M_(n) after accounting for the left over fractionalpart, d_(n), from the (n-1)-th interval, viz.,

    S.sub.n =[M.sub.n +d.sub.n ]                               (1)

and

    d.sub.n+1 =d.sub.n +M.sub.n -S.sub.n                       (2)

where [a] denotes the largest integer less than or equal to a. Since foraccurate clocks, the range of M_(n), is very tightly constrained, i.e.,M_(max) -M_(min) =2y<M_(n), the variation in S_(n) is also smaller thanits magnitude. It follows from Equation (1) that

    [M.sub.min +d.sub.n ]≧S.sub.n ≧[M.sub.max +d.sub.n ](3)

Since the maximum and minimum of d_(n) are 1 and 0 respectively, S_(n)is bounded by,

    [M.sub.min ]≧S.sub.n ≧[M.sub.max ]+1         (4)

This implies, that the most significant portion of S_(n) carries noinformation and it is necessary to transmit only its least significantportion. This, therefore, is the essential concept of the RTS. Theminimum resolution required to represent the residual part of S_(n)unambiguously is a function of N, the ratio of the network derivedfrequency to the service frequency, and the service clock tolerance, ±ε.The maximum deviation, y, between the nominal number of derived networkclock pulses in an RTS period, M_(nom), and the maximum or minimumvalues of M (M_(max) or M_(min)) is given by, ##EQU2## where M_(nom)equals ##EQU3##

A specific numerical example can be considered for clarity ofunderstanding. As illustrative derived network clock frequency andservice clock frequencies could be given by f_(nx) =155.52 MHZ (forx=1), and f_(s) =78.16 MHz (nominal), respectively. A typical RTSsampling period (N) is 3008, which corresponds to a period of 8 cellsand a 47-octet payload per cell (47 bytes/cell×8 bits/byte×8 cells perRTS period). Using these numbers, M_(nom) =5985.2119. If it is furtherreasonable to assume that the service clock tolerance is 200 parts permillion, i.e., ±200×10⁻⁶. From equation (5), therefore, y=1.197, whichdemonstrates that it is superfluous to transmit the full S_(n) in eachRTS sampling period and transmission of the last few (P) bits of S_(n)is sufficient. This P-bit sample is the Residual-TS (RTS).

FIG. 2 is a block diagram of the source node of an ATM network showingapparatus for generating and transmitting the RTS. The basic networkclock, C, shown at 10, serves as the reference for timing of all nodesof the synchronous network being here considered. This clock, having afrequency f_(n), is divided in frequency by a rational factor x by adivider 11 to produce a derived network clock having a frequency f_(nx).Preferably, x would be an integer value. The dividing factor is chosenso that the P bits available can unambiguously represent the number ofderived network clock cycles within an RTS period. In the case where##EQU4## is less than or equal to two, as in the example above, it canbe shown that a 3-bit RTS is sufficient.

The derived network clock, f_(nx), drives a P-bit counter, which iscontinuously counting these derived network clock pulses, modulo 2^(P).The service clock, f_(s), on lead 13, which is derived from the servicedata signal (not shown) to be transmitted over the ATM network, isdivided in frequency by N, the desired RTS period in units of f_(s)cycles, by divide-by N circuit 14. As shown in FIG. 2, the output ofdivider 14 is a pulse signal in which T_(n) is its n-th period. At everyT seconds (N source clock cycles) latch 15 samples the current count ofcounter 12, which is then the P-bit RTS to be transmitted. Asaforedescribed, this number represents the residual part of S_(n) and isall that is necessary to be transmitted to recover the source clock atthe destination node of the network.

Each successive RTS is incorporated within the ATM adaptation layeroverhead by AAL processor 16. The associated data to be transmitted (notshown) is also processed by processor 16 to form the payload of thecells, which are then assembled by an ATM assembler 17, which adds anATM header for transmission over the network 18.

With reference again to the previous example, a four-bit counter (P=4)can be assumed to be used. Since M_(nom) =5985.2119 and 5985.2119(modulo 16)=1.2119, a typical RTS output sequence when the source is atnominal frequency will be as follows;

    . . . 5,6,7,9,10,11,12,13,15,1,2, . . .

Since the counter 16, in effect, quantizes by truncation, the RTSchanges only by integer values. The changes in RTS are such that theiraverage is exactly equal to M_(nom) (modulo 2^(P)). In this example, thechanges are either 1 or 2 with the change of 2 occurring either every 4or 5 RTSs in such a way that the average interval is 1/0.2119=4.7198. Ingeneral, successive RTSs are related by

    RTS.sub.n+1 =RTS.sub.n +S.sub.n =RTS.sub.n +[d.sub.n +M.sub.n ](modulo 2.sup.P)                                                  (6)

In order to guarantee that no information is lost due to the moduloarithmetic, i.e., that the transmitted RTS represents S_(n)unambiguously, it can be seen from equation (4) that the number of bitsused for transmission must satisfy:

    2.sub.P ≧[M.sub.max ]-[M.sub.min ]+2                (7)

Thus, in the example above, the number of bits allocated to the RTS mustbe 3 or greater. It can be noted that the number of bits necessary tounambiguously represent the number of derived network clock cycleswithin the RTS period is substantially less than the number of bits thatwould be required to represent the absolute number of clock cycleswithin the same interval. In the example above, for example, a 13-bitnumber would be required to represent M_(nom).

If equation (7) is satisfied, knowledge of M_(nom) in the receiver atthe destination node along with the received RTSs can be used toreproduce the service clock from the synchronous network clock. FIG. 3shows one receiver implementation for reproducing the service clock fromthe received RTSs. At the receiver the common network clock 10 isavailable as it was at the transmitter. As in the transmitter, a divider31 divides the network clock frequency, f_(n) by the same factor of x asdivider 11 in the source node, to produce the same derived network clocksignal having a frequency f_(nx) as was used by the transmitter at thesource node of FIG. 2.

In a structure paralleling the transmitter in FIG. 2, a disassembler 32processes the ATM headers received from the network 18 and passes thepayload to an AAL processor 33. In addition to extracting thetransmitted data (not shown), processor 33 extracts the periodictransmitted RTSs, which are sequentially stored in a FIFO 34, which isused to absorb the network cell jitter. The earliest received RTS inFIFO 34 is compared by P-bit comparator 35 with the count of a freerunning P-bit counter 36, driven by the derived network clock, f_(nx).Whenever the output of counter 36 matches the current RTS, comparator 35generates a pulse. Since counter 36 is a modulo 2_(P) counter, the RTSin FIFO 34 matches the count of counter 36 every 2_(P) derived networkclock pulses, f_(nx). The output of comparator 35 thus consists of atrain of pulses that are separated, except for the first pulse, by 2_(P)cycles of the derived network clock. In order to select the output pulseof comparator 35 that corresponds to the end of the fixed period of thetransmitted service clocks, which is the period per RTS to be recovered,gating circuitry 37 is employed. Gating circuitry 37, which includes acounter 38, a gating signal generator 39, and an AND gate 40, gates onlythat pulse output of comparator 35 produced after counting, from thelast gated output pulse, a minimum number, M_(l), of derived networkclock cycles. This minimum number, M_(l), is given by:

    M.sub.l =[M.sub.nom ]-.sup.(P-1)                           (8)

This ensures that [M_(max) ]-2_(P) <M_(l) <[M_(min) ], and thus thegating pulse is guaranteed to select the correct RTS.

The gating function is best explained in conjunction with the timingdiagrams of FIG. 4. Initially, it can be assumed that gating signalgenerator 39 is set to keep AND gate 40 open. Comparator 35 compares thefirst RTS in FIFO 34 with the free-running count of counter 36. When thecount of counter 36 matches this first RTS, shown in FIG. 4 as "2",comparator 35 produces a pulse which is gated through AND gate 40. Thisgated output pulse resets gating signal generator 39 thereupon turningoff AND gate 40, resets the counter of counter 38 to zero, and reads thenext stored RTS, "5", in FIFO 34. When counter 36 reaches the count of"5", comparator 35 produces another output pulse. AND gate 40, however,is OFF and remains off until counter 38 counts M_(l) derived networkclock cycles. Therefore, as noted in FIG. 4, all the subsequent matchesof the RTS, "5" and the count of counter 36, which occur every 2_(P)derived network clock cycles, are blocked by AND gate 40. Thesesubsequent pulses are blocked until counter 38 reaches a count of thatminimum number of clock cycles that can comprise the fixed interval tobe recovered from the RTS. After counting M_(l) derived network clockcycles, counter 38 generates a pulse which signals gating signalgenerator 39 to open AND gate 40. The next pulse produced by comparator35 upon the match between the RTS in FIFO 34 and the count of counter 36is gated through AND gate 40. This pulse, as before, resets counter 38,resets gating signal generator 39, and reads-in the next stored RTS tothe output of FIFO 34. The resultant time difference between outputpulses of AND gate 40 is the desired fixed time interval, S_(n), to berecovered from the transmitted RTSs. As previously defined in equation(1), S_(n) is the truncated value in the nth interval, after accountingfor a left over portion from the (n-1)-th interval, of the actual numberof derived network clock cycles within the fixed interval defined by Nsource clock cycles. As can be noted, S_(n) modulo (2^(P)) is equal tothe difference of the RTSs associated with the pulses matched bycomparator 35 right before and right after the reset. Thus in FIG. 4,for the n-th period, this is the difference between "5" and "2", or "3",and for the (n+1)-st period, this is the difference between "9" and "5"or "4". The resultant pulse train at the output of gating circuitry 37can be seen to duplicate the signal at the source node of the network,which is defined by N service clock cycles, as modified by thequantization effect of the RTSs. This pulse stream is input to amultiply-by N phase-locked loop 41 which multiplies the frequency by thefactor of N and smooths out the variation of the reproduced periods. Theresultant output clock signal, f_(r), is the reproduced service timingsignal, which can be employed by the circuitry at the destination node.

The above-described embodiment is illustrative of the principles of thepresent invention. Other embodiments could be devised by those skilledin the art without departing from the spirit and scope of the presentinvention.

What is claimed is:
 1. A method of recovering, at a destination node ofa packet-based telecommunications network, the timing clock of a serviceinput at a source node of said packet-based telecommunications network,the destination node and the source node having a common network clock,comprising the steps of:(a) at the source node, dividing the timingclock of the service input by a factor of an integer N to form residualtime stamp (RTS) periods; (b) at the source node, counting the networkclock cycles modulo 2^(P), where 2_(P) is less than the number ofnetwork clock cycles within an RTS period and P is chosen so that the2_(P) counts uniquely and unambiguously represent the range of possiblenetwork clock cycles within an RTS period; (c) transmitting from thesource node to the destination node an RTS at the end of each RTS periodthat is equal to the modulo 2_(P) count of network clock cycles at thattime; (d) determining from the RTSs received at the destination node,the number of network clock cycles in each RTS period; (e) generating apulse signal from the network clock at the destination node in which theperiod between each pulse in the pulse signal equals the determinednumber of network clock cycles in the corresponding RTS period; and (f)multiplying the frequency of the pulse signal generated in step (e) bythe same factor of an integer N used in step (a) to recover the timingclock of the service input.
 2. The method of claim 1 wherein the networkclock frequency is less than or equal to twice the service clockfrequency.
 3. A method of recovering, at a destination node of apacket-based telecommunications network, the timing clock of a serviceinput at a source node of said packet-based telecommunications network,the destination node and the source node having a common network clock,comprising the steps of:(a) at the source node, dividing the timingclock of the service input by a factor of an integer N to form residualtime stamp (RTS) periods; (b) at the source node, dividing the networkclock by a rational factor to form a derived network clock; (c) at thesource node, counting the derived network clock cycles modulo 2^(P),where 2_(P) is less than the number of derived network clock cycleswithin an RTS period and P is chosen so that the 2_(P) counts uniquelyand unambiguously represent the range of possible derived network clockcycles within an RTS period; (d) transmitting from the source node tothe destination node an RTS at the end of each RTS period that is equalto the modulo 2_(P) count of derived network clock cycles at that time;(e) at the destination node, dividing the network clock by the samerational factor used at the source node to form a derived network clockequal to the derived network clock at the source node; (f) determiningfrom the RTSs received at the destination node, the number of derivednetwork clock cycles in each RTS period; (g) generating a pulse signalfrom the derived network clock at the destination node in which theperiod between each pulse in the pulse signal equals the determinednumber of derived network clock cycles in the corresponding RTS period;and (h) multiplying the frequency of the pulse signal generated in step(g) by the same factor of an integer N used in step (a) to recover thetiming clock of the service input.
 4. The method of claim 3 wherein thederived network clock frequency is less than or equal to twice theservice clock frequency.
 5. Apparatus for recovering, at a destinationnode of a packet-based telecommunications network, the timing clock of aservice input at a source node of said packet-based telecommunicationsnetwork, the destination node and the source node having a commonnetwork clock, comprising at the source node:dividing means for dividingthe timing clock of the service input by a factor of an integer N toform residual time stamp (RTS) periods; counting means connected to thenetwork clock for counting network clock cycles modulo 2^(P), where2_(P) is less than the number of network clock cycles within an RTSperiod and P is chosen so that the 2_(P) counts uniquely andunambiguously represent the range of possible network clock cycleswithin an RTS period; and transmitting means, responsive to the RTSperiods formed by said dividing means and the count of said countingmeans, for transmitting over the telecommunications network an RTS atthe end of each RTS period that is equal to the modulo 2^(P) count ofnetwork clock cycles at that time; and comprising at the destinationnode: receiving means for receiving the RTSs transmitted over thetelecommunications network by said transmitting means; converting meansresponsive to the received RTSs and the network clock for converting thereceived RTSs into a pulse signal in which the periods between pulsesare determined from the numbers of network clock cycles associated withthe counts of network clock cycles within said RTS periods; and meansfor multiplying the frequency of the pulse signal generated by saidconverting means by the same factor of an integer N used in saiddividing means for recovering the timing clock of the service input. 6.Apparatus in accordance with claim 5 wherein the network clock frequencyis less than or equal to twice the service clock frequency.
 7. Apparatusin accordance with claim 5 wherein said converting means comprises:meansfor sequentially storing the received RTSs; means for counting networkclock cycles modulo 2_(P) ; comparing means for comparing the modulo2_(P) count of network clock cycles with a stored RTS and for generatinga pulse each time the count of network clock cycles matches the RTS; andgating means for gating to said multiplying means, for each sequentiallyreceived and stored RTS, the pulse produced by said comparing means thatoccurs after the counting means counts, starting-in-time from theprevious gated pulse, a number of network clock cycles that is greaterthan a predetermined minimum absolute number of network clock cyclesthat can occur within any RTS period.
 8. Apparatus for recovering, at adestination node of a packet-based telecommunications network, thetiming clock of a service input at a source node of said packet-basedtelecommunications network, the destination node and the source nodehaving a common network clock, comprising at the source node:firstdividing means for dividing the timing clock of the service input by afactor of an integer N to form residual time stamp (RTS) periods; seconddividing means for dividing the network clock by a rational factor toform a derived network clock; counting means connected to the networkclock for counting derived network clock cycles modulo 2^(P), where2_(P) is less than the number of derived network clock cycles within anRTS period and P is chosen so that the 2_(P) counts uniquely andunambiguously represent the range of possible derived network clockcycles within an RTS period; and transmitting means, responsive to theRTS periods formed by said first dividing means and the count of saidcounting means, for transmitting over the telecommunications network anRTS at the end of each RTS period that is equal to the modulo 2^(P)count of derived network clock cycles at that time; and comprising atthe destination node: receiving means for receiving the RTSs transmittedover the telecommunications network by said transmitting means; meansfor dividing the network clock by the same rational factor used at thesource node to form a derived network clock; converting means responsiveto the received RTSs and the derived network clock for converting thereceived RTSs into a pulse signal in which the periods between pulsesare determined from the numbers of derived network clock cyclesassociated with the counts of derived network clock cycles within saidRTS periods; and means for multiplying the frequency of the pulse signalgenerated by said converting means by the same factor of an integer Nused in said first dividing means for recovering the timing clock of theservice input.
 9. Apparatus in accordance with claim 8 wherein thederived network clock frequency is less than or equal to twice serviceclock frequency.
 10. Apparatus in accordance with claim 8 wherein saidconverting means comprises:means for sequentially storing the receivedRTSs; means for counting derived network clock cycles modulo 2_(P) ;comparing means for comparing the modulo 2_(P) count of derived networkclock cycles with a stored RTS and for generating a pulse each time thecount of derived network clock cycles matches the RTS; and gating meansfor gating to said multiplying means, for each sequentially received andstored RTS, the pulse produced by said comparing means that occurs afterthe counting means counts, starting-in-time from the previous gatedpulse, a number of derived network clock cycles that is greater than apredetermined minimum absolute number of derived network clock cyclesthat can occur within any RTS period. .Iadd.11. Apparatus for generatinga representation of the relationship between the timing clock of aservice input, at a source node of a packet-based telecommunicationsnetwork, and a network clock, the apparatus comprising: (a) means, atthe source node, for defining a residual time stamp (RTS) period as anintegral number N of source-node service clock cycles; (b) means, at thesource node, for defining a derived network clock frequency f_(nx) froma network frequency f_(n) where f_(nx) =f_(n) /x, x is a rationalnumber, and f_(nx) is less than or equal to twice the service clockfrequency; (c) means, at the source node, for counting the derivednetwork clock cycles modulo 16 in an RTS period and; (d) means fortransmitting from the source node an RTS that is equal to the modulo 16count of derived network clock cycles in the RTS period..Iaddend..Iadd.12. Apparatus for recovering, at a destination node of apacket-based telecommunications network, the timing clock of a serviceinput at a source node of the packet-based telecommunications network,wherein the destination and source nodes have a common network clockdivided network clock and wherein the service node generates a residualtime stamp (RTS) signal equal to a modulo 16 count of cycles based onthe network clock; the apparatus comprising:means for receiving the RTSsignal; means for determining the number of network cycles in an RTSperiod from the RTS signal; and means responsive to the determiningmeans for generating a clock signal which represents a recovery of thetiming clock of the service input. .Iaddend..Iadd.13. Apparatus forgenerating a representation of a timing clock of a service input at asource node of a packet-based telecommunications network, wherein acommon network clock or divided network clock is provided for the sourcenode and a destination node; the apparatus comprising: (a) means fordefining a time interval by a fixed number of service clock cycles; and(b) means for generating a digital representation of a quantizeddifference between an actual number of network clock cycles within thetime interval and an expected number of network clock cycles within thetime interval, the difference being within a defined time windowcorresponding to a frequency variation of the source-node service clock..Iaddend..Iadd.14. The apparatus of claim 13, wherein the digitalrepresentation represents a chosen number of the least significant bitsof the quantized actual number, the chosen number being sufficient torepresent a range of frequency deviations of the source-node serviceclock variation. .Iaddend..Iadd.15. The apparatus of claim 14 whereinthe chosen number is
 4. .Iaddend..Iadd.16. Apparatus for recovering, ata destination node of a packet-based telecommunications network, thetiming clock of a service input at a source node of said network,wherein a common network clock or divided network clock is provided forthe destination node and the source node and a time interval is definedby a fixed rational number of source-node service clock cycles; theapparatus comprising:means for receiving generating a digitalrepresentation of a quantized difference between an actual number ofnetwork clock cycles within the time interval and an expected number ofnetwork clock cycles within the time interval, the difference beingwithin a defined time window corresponding to a frequency variation ofthe source-node service clock; and means for recovering the source-nodeservice clock at the destination node by constructing a timing signal atthe destination node based on a received representation of the networkcycle difference. .Iaddend..Iadd.17. Apparatus for reconstructing, at adestination node of a packet-based telecommunications network, a timingclock of a service input at a source node of the network, wherein acommon network clock or divided network clock is provided for thedestination node and the source node and wherein the reconstruction isbased on successive modulo 2^(P) numerical representations of the numberof network clock cycles within corresponding successive predeterminedtime periods, each of the numerical representations being received fromthe source node and being less than the actual number of network clockcycles within its corresponding time period; the apparatus comprising:means for receiving the numerical representations in succession at thedestination node; means for converting the received numericalrepresentations into successive fixed time intervals, wherein eachsuccessive interval corresponds to the number of network clock cycles ina corresponding one of the predetermined time periods; and means forrecovering the source-node service clock from the fixed time intervals..Iaddend..Iadd.18. The apparatus of claim 17, wherein the convertingmeans further comprises: means for sequentially storing the successivemodulo 2^(P) numerical representations; means for comparing thesuccessive numerical representations with a modulo 2^(P) count of thenetwork clock cycles at the destination node to generate a comparisonsignal for each match between the numerical representation and themodulo 2^(P) count at the destination node; and means for successivelyselecting a proper comparison signal by waiting until a minimum numberof network clock cycles has occurred. .Iaddend..Iadd.19. A method forgenerating a signal at a source node for use in recovering a source-nodeservice clock at a destination node in a packet-based telecommunicationsnetwork, wherein a common network clock or divided network clock isprovided for the source and destination nodes; the steps of the methodcomprising:defining a time interval by a fixed number of cycles of thesource-node service clock; determining an actual number of cycles of thenetwork clock within the time interval; determining a numericaldeviation of the number of actual network clock cycles from anothernumber of network clock cycles that would occur if the source-nodeservice clock frequency were nominal; and generating a digital signalrepresenting the numerical deviation for transmission through thenetwork to the destination node. .Iaddend..Iadd.20. A method forrecovering a source-node service clock at a destination node in apacket-based telecommunications network, wherein a common network clockor divided network clock is provided for the source and destinationnodes, wherein an actual time interval is defined by a fixed number ofcycles of the source-node service clock, and wherein a number of actualcycles of the network clock within the actual time interval and anumerical deviation of the number of actual network clock cycles fromanother number of network clock cycles known nominally to be within thetime interval are determined; the steps of the method comprising:receiving a digital signal representing the numerical deviationtransmitted through the network from the source node; and generating atiming signal corresponding to the source-node service clock on thebasis of the digital signal representing the numerical deviation..Iaddend..Iadd.21. A method for recovering, at a destination node of apacket-based telecommunications network, a timing clock of a serviceinput at a source node of the packet-based telecommunications network,wherein a common network clock or divided network clock is provided forthe destination node and the source node; the steps of the methodcomprising: defining a time interval by a fixed number of cycles of thesource-node service clock; determining an actual number of cycles of thenetwork clock within the time interval; determining a numericaldeviation of the number of actual network clock cycles from anothernumber of network clock cycles that would occur within the time intervalif the source-node service clock frequency were nominal; generating adigital signal representing the numerical deviation; transmitting thedigital signal to the destination node; and generating a timing signalat the destination node corresponding to the source node service clockon the basis of the digital signal and a signal from the network clock..Iaddend..Iadd.22. The method of claim 21 wherein the numericaldeviation is determined as a function of the fixed number of source-nodeservice clock cycles, the frequencies of the network clock and thesource-node service clock, and a frequency variation of the source-nodeservice clock. .Iaddend..Iadd.23. The method of claim 21 furtherincluding the step of employing a modulo 2^(P) counter to generate arepresentation of the numerical deviation. .Iaddend..Iadd.24. Apparatusfor generating a signal at a source node for use in recovering asource-node service clock at a destination node in a packet-basedtelecommunications network, wherein a common network clock or dividednetwork clock is provided for the source and destination nodes; theapparatus comprising:means for defining a time interval by a fixednumber of cycles of the source-node service clock; means for determininga number of actual cycles of the network clock within the time interval;means for determining a numerical deviation of the number of actualnetwork clock cycles from another number of network clock cycles thatwould occur within the time interval if the source-node clock frequencywere nominal; and means for generating a digital signal representing thenumerical deviation for transmission through the network to thedestination node. .Iaddend..Iadd.25. The apparatus of claim 24 whereinthe numerical deviation is determined as a function of the fixed numberof source-node service clock cycles, and frequencies of the networkclock and the source-node service clock, and a nominal frequency of thesource-node service clock. .Iaddend..Iadd.26. The apparatus of claim 24wherein the numerical deviation determining means includes a modulo2^(P) counter which generates the numerical deviation..Iaddend..Iadd.27. The apparatus of claim 26 wherein a value of 2^(P) is16. .Iaddend..Iadd.28. Apparatus for recovering a source-node clock at adestination node in a packet-based telecommunications network, wherein acommon network clock or divided network clock is provided for the sourceand destination nodes and wherein a time interval is defined by a fixednumber of cycles of the source-node service clock, and wherein a numberof actual cycles of the network clock within the time interval and anumerical deviation of the number of actual network clock cycles fromanother number of network clock cycles that would occur within the timeif the source-node service clock frequency were nominal;means forreceiving a digital signal representing the numerical deviationtransmitted through the network from the source node; and means forgenerating a timing signal corresponding to the source-node serviceclock on the basis of the digital signal representing the numericaldeviation. .Iaddend..Iadd.29. Apparatus for recovering, at a destinationnode of a packet-based telecommunications network, a timing clock of aservice input at a source node of the packet-based telecommunicationsnetwork, wherein a common network clock or divided network clock isprovided for the destination node and the source node; the apparatuscomprising: means for defining a time interval by a fixed number ofcycles of the source-node service clock; means for determining a numberof actual cycles of the network-clock within the time interval; meansfor determining a numerical deviation of the number of actual networkclock cycles from another number of network clock cycles that wouldoccur within the time interval if the source-node service clockfrequency were nominal; means for generating a digital signalrepresenting the numerical deviation; means for transmitting the digitalsignal to the destination node; and means for generating a timing signalat the destination node corresponding to the source-node service clockon the basis of the digital signal and a signal from the network clock..Iaddend..Iadd.30. The apparatus of claim 29 wherein the numericaldeviation is determined as a function of the fixed number of source-nodeservice clock cycles, frequencies of the network clock and thesource-node service clock, and a nominal frequency of the source-nodeservice clock. .Iaddend..Iadd.31. The apparatus of claim 29 wherein thenumerical deviation determining means includes a modulo 2^(P) counterwhich generates the numerical deviation. .Iaddend..Iadd.32. Theapparatus of claim 29 wherein means are provided for carrying anyfractional network cycle in any time interval for network cycle countingby the modulo 2^(P) counter for counting the next time interval..Iaddend..Iadd.33. A method for generating a representation of therelationship between the timing clock of a service input, at a sourcenode of a packet-based telecommunications network, and a network clock,the method comprising the steps of:(a) defining, at the source node, aresidual time stamp (RTS) period as an integral number N of source-nodeservice clock cycles; (b) defining, at the source node, a derivednetwork clock frequency f_(nx) from a network frequency f_(n) wheref_(nx) =f_(n) /x, x is a rational number, and f_(nx) is less than orequal to twice the service clock frequency; (c) counting, at the sourcenode, the derived network clock cycles modulo 16 in an RTS period; and(d) transmitting from the source node an RTS that is equal to the modulo16 count of derived network clock cycles in the RTS period. .Iaddend.